EVALUATION OF FIXED PRIORITY ARBITER AND ROUND ROBIN ON FPGA SPARTAN 3E

Abstract

In System on chip (SoC), having simultaneous access from multiple Sources or Masters to the same Slave is common. However, one Slave cannot respond to all accesses at the same time but can only respond sequentially to each access in a certain order. Determining which access to execute first, which access to execute after is called "access arbitration". The component that performs the "access arbitration" function is often called an Arbiter. In this paper, the authors design a fixed-priority arbiter and a Round Robin arbiter that performs arbitration for four Masters and one Slave. These two arbiters will be combined and designed using Verilog on Xilinx ISE Design Suite 14.7 software. The design of the two arbiters after synthesis will be checked and evaluated by testcases to compare the algorithm and arbitration speed. Finally, the authors will implement two arbiters on FPGA Xilinx Spartan 3E to check the simulation results.