DESIGN A LOW POWER, 100dB OPERATIONAL AMPLIFIER USING CMOS TECHNOLOGY

Abstract

The requirement for reduced size and long battery life for portable
applications in all based on the conditions has accelerated the trend toward low
power silicon chip systems. The supply voltage is being reduced in order to
reduce the system’s overall power usage. The op-amp (OPA) design for highspeed applications requires proper selection of biasing, logic style and
compensation techniques as the technology is scaling down. This paper presents
a design of the two-stage op-amps (OPA) using 90nm process with functional
verification and gain calculations. In order to improve stability, the
compensation technique is added to OPA to improve performance metrics.
According to simulation results, the designed OPA obtains a gain of 131dB with
60 degrees phase margin. The OPA achieves a gain-bandwidth (GBW) of
1.26MHz by consuming a current of 2.56µA from a 1.8V supply.